wordpress搜索全站,燕子项目网,东莞公司官网推广,网站仿静态和静态的区别CPU物理核及L1、L2、L3及缓存 CPU缓存 CPU 缓存是一种用于存储临时数据以提高计算机程序性能的内存层次结构。它通常分为三个层次#xff1a;L1#xff08;一级#xff09;、L2#xff08;二级#xff09;和L3#xff08;三级#xff09;缓存。缓存大小是CPU的重…CPU物理核及L1、L2、L3及缓存 CPU缓存 CPU 缓存是一种用于存储临时数据以提高计算机程序性能的内存层次结构。它通常分为三个层次L1一级、L2二级和L3三级缓存。缓存大小是CPU的重要指标之一并且缓存的结构和大小对CPU速度的影响非常大CPU内缓存的运行频率极高一般是同处理器同频运行工作效率远远大于系统内存和硬盘。实际工作时CPU经常需要重复读取同样的数据块而缓存容量的增大能大幅提升CPU内部读取数据的命中率不需要到内存或者硬盘上寻找从而提升系统新能。
L1 Cache一级缓存 L1 缓存是距离处理器核心最近的缓存层用于存储最常用的数据和指令。通常比较小但速度非常快。
数据缓存L1 DCache 数据缓存存储处理器核心正在处理的数据
指令缓存L1 ICache 指令缓存则存储处理器正在执行的指令。
L2 Cache二级缓存 L2 缓存位于 L1 缓存和主内存之间用于存储更多的数据和指令以便在 L1 缓存未命中时提供更多的备份。比 L1 大速度较快但比 L1 缓存慢。
L3 Cache三级缓存 L3 缓存是位于处理器核心之间的共享缓存多个处理器核心可以共享相同的 L3 缓存。这有助于减少核心之间的数据传输时延。比 L2 大通常比 L1 和 L2 慢一些。
CacheLine
缓存行Cache Line 缓存通常以固定大小的缓存行为单位进行管理。当 CPU 访问内存时它不是一次性读取一个字节而是一次性读取一整个缓存行。这有助于提高数据局部性因为相邻的数据很可能在近期内被使用到。每次CPU从内存获取数据或者L2从L3获取数据都是按照Cache Line大小读取的即是只读取一个bit或者一个bytesCPU也是读取一个Cache Line的大小然后放到缓存里面存储。
缓存行Cache Line查看大小
#cat cpu0/cache/index0/coherency_line_size
64
物理CPU
物理CPU( Physical Central Processing Unit) 中央处理单元CPU不等于物理核更不等于逻辑核,主板上真正安装的CPU的个数
查看物理CPU方法
# cat /proc/cpuinfo |grep physical id|sort |uniq|wc -l2
或
# cat /proc/cpuinfo | grep physical id | sort -uphysical id : 0physical id : 1
或
# cat /proc/cpuinfo | grep physical id | sort -u | wc -l2
物理核
物理核(physical core/processor) 可以看的到的真实的cpu核有独立的电路元件以及L1,L2缓存可以独立地执行指令。
查看物理核的方法 # cat /proc/cpuinfo| grep cpu cores| uniqcpu cores : 16或# cat /proc/cpuinfo |grep cores|uniqcpu cores : 16
逻辑核
逻辑核( logical core/processorLCPU) 在同一个物理核内逻辑层面的核。比喻像动画片一样我们看到的“动画”其实是一帧一帧静态的画面24帧/s连起来就骗过了人类的眼睛看起来像动起来一样。逻辑核也一样物理核通过高速运算让应用程序以为有两个cpu在运算。
查看逻辑核的方法
# cat /proc/cpuinfo| grep processor| wc -l64
超线程
超线程( Hyper-threading HT) 超线程可以在一个逻辑核等待指令执行的间隔(等待从cache或内存中获取下一条指令)把时间片分配到另一个逻辑核。高速在这两个逻辑核之间切换让应用程序感知不到这个间隔误认为自己是独占了一个核。
判断是否开启超线程方法 多个逻辑CPU的physical id和core id均相同说明开启了超线程
逻辑CPU个数 物理CPU个数 * CPU内核数 -----》 开启了超线程
逻辑CPU个数 物理CPU个数 * CPU内核数 -----》 没有开启超线程
物理核、逻辑核和超线程关系 一个CPU可以有多个物理核。如果开启了超线程一个物理核可以分成n个逻辑核n为超线程的数量。
总核数 物理CPU个数 X 每颗物理CPU的核数
总逻辑CPU数 物理CPU个数 X 每颗物理CPU的核数 X 超线程数
查看CPU信息
# cat /proc/cpuinfo | grep name | cut -f2 -d: | uniq -c64 Intel(R) Xeon(R) Gold 6242 CPU 2.80GHz
判断CPU是32还是64位运行模式
# getconf LONG_BIT
64 物理CPU上面封装的逻辑处理器即超线程后的CPU个数 # cat /proc/cpuinfo | grep siblings
siblings : 32
siblings : 32
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查看主板型号
# dmidecode |grep -A16 System Information
System InformationManufacturer: New H3C Technologies Co., Ltd.Product Name: UniServer R4900 G3Version: To be filled by O.E.M.Serial Number: xxxxx35A2CT6215F0012DUUID: xxxx5-xxx-xxx-xxx-xxxWake-up Type: Power SwitchSKU Number: 0Family: RackHandle 0x0002, DMI type 2, 15 bytes
Base Board InformationManufacturer: H3CProduct Name:xxxxxVersion: xxxxxxSerial Number: xxxxxxAsset Tag: To be filled by O.E.M.
查看cpu信息
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 64
On-line CPU(s) list: 0-63
Thread(s) per core: 2
Core(s) per socket: 16
Socket(s): 2
NUMA node(s): 2
Vendor ID: GenuineIntel
CPU family: 6
Model: 85
Model name: Intel(R) Xeon(R) Gold 6242 CPU 2.80GHz
Stepping: 7
CPU MHz: 1199.781
CPU max MHz: 3900.0000
CPU min MHz: 1200.0000
BogoMIPS: 5600.00
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 1024K
L3 cache: 22528K
NUMA node0 CPU(s): 0-15,32-47
NUMA node1 CPU(s): 16-31,48-63
Flags: xxxxxxxxxxxxxxxxxxxxxxxxxxx查看CPU缓存信息
# lscpu | grep L1d -A3
L1d cache: 32K
L1i cache: 32K
L2 cache: 1024K
L3 cache: 22528K
CPU的TBL
虚拟内存 在用户的空间里每个进程都有自己独立的地址空间每个进程都有完全独立的4GB虚拟内存它们看到的都是操作系统虚拟出来的地址空间。但是虚拟地址最终是要映射到实际内存的物理地址上进行操作的。系统会通过页表机制来实现进程的虚拟地址到物理地址的映射。
页表管理 页表管理主要有页大小和页表级数
获取页大小指令
# getconf PAGESIZE 4096
表示4KB
页表级数 页表级数越少虚拟地址到物理地址的映射越快但是需要管理的页表项也越多能支持的地址空间有限反之页表级数越多需要存储的页表数据越少能支持的地址空间越大但是虚拟地址到物理地址的映射会越慢。
32位系统一般采用2级页表32位地址空间目前主流的一般都是采用4级页表支持48位地址空间
PGD(Page Global Directory)页全局目录管理地址空间的第39~47位
PUD(Page Upper Directory)页上级目录管理地址空间的第30~38位
PMD(Page Middle Directory)页中间目录管理地址空间第21~29位
PTE(Page Table Entry)页表项管理地址空间的第12~20位
页表机制存在的问题 在访问一个虚拟地址上的变量值之前需要将虚拟地址映射为物理地址每一级的页表都是存储在内存中的在完成一个虚拟地址转换的过程中需要将当前虚拟地址对应的四个页表全部找出才能完成虚拟地址到物理地址的转化这就表示一次内存IO进虚拟地址到物理地址的转化就需要去内存查4次页表在这种情况下就引入了TBL缓存
TBLTranslation Lookaside BUffer 用于加快虚拟地址到物理地址转换速度的缓存访问速度和寄存器访问差不多比CPU的L1缓存访问还快。
查看系统TLB缓存大小指令
cpuid
如果不存在ubuntu可以通过apt install cpuid安装
CPU 0:vendor_id GenuineIntelversion information (1/eax):processor type primary processor (0)family Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)model 0xc (12)stepping id 0x3 (3)extended family 0x0 (0)extended model 0x3 (3)(simple synth) Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nmmiscellaneous (1/ebx):process local APIC physical ID 0x0 (0)cpu count 0x1 (1)CLFLUSH line size 0x8 (8)brand index 0x0 (0)brand id 0x00 (0): unknownfeature information (1/edx):x87 FPU on chip truevirtual-8086 mode enhancement truedebugging extensions truepage size extensions truetime stamp counter trueRDMSR and WRMSR support truephysical address extensions truemachine check exception trueCMPXCHG8B inst. trueAPIC on chip trueSYSENTER and SYSEXIT truememory type range registers truePTE global bit truemachine check architecture trueconditional move/compare instruction truepage attribute table truepage size extension trueprocessor serial number falseCLFLUSH instruction truedebug store falsethermal monitor and clock ctrl falseMMX Technology trueFXSAVE/FXRSTOR trueSSE extensions trueSSE2 extensions trueself snoop truehyper-threading / multi-core supported falsetherm. monitor falseIA64 falsepending break event falsefeature information (1/ecx):PNI/SSE3: Prescott New Instructions truePCLMULDQ instruction true64-bit debug store falseMONITOR/MWAIT falseCPL-qualified debug store falseVMX: virtual machine extensions trueSMX: safer mode extensions falseEnhanced Intel SpeedStep Technology falsethermal monitor 2 falseSSSE3 extensions truecontext ID: adaptive or shared L1 data falseFMA instruction trueCMPXCHG16B instruction truexTPR disable falseperfmon and debug falseprocess context identifiers truedirect cache access falseSSE4.1 extensions trueSSE4.2 extensions trueextended xAPIC support trueMOVBE instruction truePOPCNT instruction truetime stamp counter deadline trueAES instruction trueXSAVE/XSTOR states trueOS-enabled XSAVE/XSTOR trueAVX: advanced vector extensions trueF16C half-precision convert instruction trueRDRAND instruction truehypervisor guest status truecache and TLB information (2):0x63: data TLB: 1G pages, 4-way, 4 entries0x03: data TLB: 4K pages, 4-way, 64 entries0x76: instruction TLB: 2M/4M pages, fully, 8 entries0xff: cache data is in CPUID 40xb5: instruction TLB: 4K, 8-way, 64 entries0xf0: 64 byte prefetching0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entriesprocessor serial number: 0003-06C3-0000-0000-0000-0000deterministic cache parameters (4):--- cache 0 ---cache type data cache (1)cache level 0x1 (1)self-initializing cache level truefully associative cache falseextra threads sharing this cache 0x0 (0)extra processor cores on this die 0x0 (0)system coherency line size 0x3f (63)physical line partitions 0x0 (0)ways of associativity 0x7 (7)ways of associativity 0x0 (0)WBINVD/INVD behavior on lower caches falseinclusive to lower caches falsecomplex cache indexing falsenumber of sets - 1 (s) 63--- cache 1 ---cache type instruction cache (2)cache level 0x1 (1)self-initializing cache level truefully associative cache falseextra threads sharing this cache 0x0 (0)extra processor cores on this die 0x0 (0)system coherency line size 0x3f (63)physical line partitions 0x0 (0)ways of associativity 0x7 (7)ways of associativity 0x0 (0)WBINVD/INVD behavior on lower caches falseinclusive to lower caches falsecomplex cache indexing falsenumber of sets - 1 (s) 63--- cache 2 ---cache type unified cache (3)cache level 0x2 (2)self-initializing cache level truefully associative cache falseextra threads sharing this cache 0x0 (0)extra processor cores on this die 0x0 (0)system coherency line size 0x3f (63)physical line partitions 0x0 (0)ways of associativity 0x7 (7)ways of associativity 0x0 (0)WBINVD/INVD behavior on lower caches falseinclusive to lower caches falsecomplex cache indexing falsenumber of sets - 1 (s) 511--- cache 3 ---cache type unified cache (3)cache level 0x3 (3)self-initializing cache level truefully associative cache falseextra threads sharing this cache 0x0 (0)extra processor cores on this die 0x0 (0)system coherency line size 0x3f (63)physical line partitions 0x0 (0)ways of associativity 0xf (15)ways of associativity 0x6 (6)WBINVD/INVD behavior on lower caches falseinclusive to lower caches truecomplex cache indexing truenumber of sets - 1 (s) 8191MONITOR/MWAIT (5):smallest monitor-line size (bytes) 0x0 (0)largest monitor-line size (bytes) 0x0 (0)enum of Monitor-MWAIT exts supported falsesupports intrs as break-event for MWAIT falsenumber of C0 sub C-states using MWAIT 0x0 (0)number of C1 sub C-states using MWAIT 0x0 (0)number of C2 sub C-states using MWAIT 0x0 (0)number of C3 sub C-states using MWAIT 0x0 (0)number of C4 sub C-states using MWAIT 0x0 (0)number of C5 sub C-states using MWAIT 0x0 (0)number of C6 sub C-states using MWAIT 0x0 (0)number of C7 sub C-states using MWAIT 0x0 (0)Thermal and Power Management Features (6):digital thermometer falseIntel Turbo Boost Technology falseARAT always running APIC timer truePLN power limit notification falseECMD extended clock modulation duty falsePTM package thermal management falseHWP base registers falseHWP notification falseHWP activity window falseHWP energy performance preference falseHWP package level request falseHDC base registers falsedigital thermometer thresholds 0x0 (0)ACNT/MCNT supported performance measure falseACNT2 available falseperformance-energy bias capability falseextended feature flags (7):FSGSBASE instructions trueIA32_TSC_ADJUST MSR supported trueSGX: Software Guard Extensions supported falseBMI instruction trueHLE hardware lock elision falseAVX2: advanced vector extensions 2 trueFDP_EXCPTN_ONLY falseSMEP supervisor mode exec protection trueBMI2 instructions trueenhanced REP MOVSB/STOSB trueINVPCID instruction trueRTM: restricted transactional memory falseQM: quality of service monitoring falsedeprecated FPU CS/DS trueintel memory protection extensions falsePQE: platform quality of service enforce falseAVX512F: AVX-512 foundation instructions falseAVX512DQ: double quadword instructions falseRDSEED instruction falseADX instructions falseSMAP: supervisor mode access prevention falseAVX512IFMA: fused multiply add falseCLFLUSHOPT instruction falseCLWB instruction falseIntel processor trace falseAVX512PF: prefetch instructions falseAVX512ER: exponent reciprocal instrs falseAVX512CD: conflict detection instrs falseSHA instructions falseAVX512BW: byte word instructions falseAVX512VL: vector length falsePREFETCHWT1 falseAVX512VBMI: vector byte manipulation falseUMIP: user-mode instruction prevention falsePKU protection keys for user-mode falseOSPKE CR4.PKE and RDPKRU/WRPKRU falseBNDLDX/BNDSTX MAWAU value in 64-bit mode 0x0 (0)RDPID: read processor D supported falseSGX_LC: SGX launch config supported falseAVX512_4VNNIW: neural network instrs falseAVX512_4FMAPS: multiply acc single prec falseDirect Cache Access Parameters (9):PLATFORM_DCA_CAP MSR bits 0Architecture Performance Monitoring Features (0xa/eax):version ID 0x1 (1)number of counters per logical processor 0x4 (4)bit width of counter 0x30 (48)length of EBX bit vector 0x7 (7)Architecture Performance Monitoring Features (0xa/ebx):core cycle event not available trueinstruction retired event not available truereference cycles event not available truelast-level cache ref event not available truelast-level cache miss event not avail truebranch inst retired event not available truebranch mispred retired event not avail trueArchitecture Performance Monitoring Features (0xa/edx):number of fixed counters 0x0 (0)bit width of fixed counters 0x0 (0)x2APIC features / processor topology (0xb):--- level 0 (thread) ---bits to shift APIC ID to get next 0x0 (0)logical processors at this level 0x1 (1)level number 0x0 (0)level type thread (1)extended APIC ID 0--- level 1 (core) ---bits to shift APIC ID to get next 0x0 (0)logical processors at this level 0x1 (1)level number 0x1 (1)level type core (2)extended APIC ID 0XSAVE features (0xd/0):XCR0 lower 32 bits valid bit field mask 0x00000007XCR0 upper 32 bits valid bit field mask 0x00000000XCR0 supported: x87 state trueXCR0 supported: SSE state trueXCR0 supported: AVX state trueXCR0 supported: MPX BNDREGS falseXCR0 supported: MPX BNDCSR falseXCR0 supported: AVX-512 opmask falseXCR0 supported: AVX-512 ZMM_Hi256 falseXCR0 supported: AVX-512 Hi16_ZMM falseIA32_XSS supported: PT state falseXCR0 supported: PKRU state falsebytes required by fields in XCR0 0x00000340 (832)bytes required by XSAVE/XRSTOR area 0x00000340 (832)XSAVE features (0xd/1):XSAVEOPT instruction trueXSAVEC instruction falseXGETBV instruction falseXSAVES/XRSTORS instructions falseSAVE area size in bytes 0x00000000 (0)IA32_XSS lower 32 bits valid bit field mask 0x00000000IA32_XSS upper 32 bits valid bit field mask 0x00000000AVX/YMM features (0xd/2):AVX/YMM save state byte size 0x00000100 (256)AVX/YMM save state byte offset 0x00000240 (576)supported in IA32_XSS or XCR0 XCR0 (user state)64-byte alignment in compacted XSAVE falsehypervisor_id VMwareVMware0x40000001 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000002 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000003 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000004 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000005 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000006 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000007 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000008 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000009 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000a 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000b 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000c 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000d 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000e 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000f 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x00000000hypervisor generic timing information (0x40000010):TSC frequency (Hz) 3392143bus frequency (Hz) 66000extended feature flags (0x80000001/edx):SYSCALL and SYSRET instructions trueexecution disable true1-GB large page support trueRDTSCP true64-bit extensions technology available trueIntel feature flags (0x80000001/ecx):LAHF/SAHF supported in 64-bit mode trueLZCNT advanced bit manipulation true3DNow! PREFETCH/PREFETCHW instructions falsebrand Intel(R) Core(TM) i7-4770 CPU 3.40GHzL1 TLB/cache information: 2M/4M pages L1 TLB (0x80000005/eax):instruction # entries 0x0 (0)instruction associativity 0x0 (0)data # entries 0x0 (0)data associativity 0x0 (0)L1 TLB/cache information: 4K pages L1 TLB (0x80000005/ebx):instruction # entries 0x0 (0)instruction associativity 0x0 (0)data # entries 0x0 (0)data associativity 0x0 (0)L1 data cache information (0x80000005/ecx):line size (bytes) 0x0 (0)lines per tag 0x0 (0)associativity 0x0 (0)size (KB) 0x0 (0)L1 instruction cache information (0x80000005/edx):line size (bytes) 0x0 (0)lines per tag 0x0 (0)associativity 0x0 (0)size (KB) 0x0 (0)L2 TLB/cache information: 2M/4M pages L2 TLB (0x80000006/eax):instruction # entries 0x0 (0)instruction associativity L2 off (0)data # entries 0x0 (0)data associativity L2 off (0)L2 TLB/cache information: 4K pages L2 TLB (0x80000006/ebx):instruction # entries 0x0 (0)instruction associativity L2 off (0)data # entries 0x0 (0)data associativity L2 off (0)L2 unified cache information (0x80000006/ecx):line size (bytes) 0x40 (64)lines per tag 0x0 (0)associativity 8-way (6)size (KB) 0x100 (256)L3 cache information (0x80000006/edx):line size (bytes) 0x0 (0)lines per tag 0x0 (0)associativity L2 off (0)size (in 512KB units) 0x0 (0)Advanced Power Management Features (0x80000007/edx):temperature sensing diode falsefrequency ID (FID) control falsevoltage ID (VID) control falsethermal trip (TTP) falsethermal monitor (TM) falsesoftware thermal control (STC) false100 MHz multiplier control falsehardware P-State control falseTscInvariant truePhysical Address and Linear Address Size (0x80000008/eax):maximum physical address bits 0x2d (45)maximum linear (virtual) address bits 0x30 (48)maximum guest physical address bits 0x0 (0)Logical CPU cores (0x80000008/ecx):number of CPU cores - 1 0x0 (0)ApicIdCoreIdSize 0x0 (0)(multi-processing synth): none(multi-processing method): Intel leaf 0xb(APIC widths synth): CORE_width0 SMT_width0(APIC synth): PKG_ID0 CORE_ID0 SMT_ID0(synth) Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm
CPU 1:vendor_id GenuineIntelversion information (1/eax):processor type primary processor (0)family Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)model 0xc (12)stepping id 0x3 (3)extended family 0x0 (0)extended model 0x3 (3)(simple synth) Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nmmiscellaneous (1/ebx):process local APIC physical ID 0x2 (2)cpu count 0x1 (1)CLFLUSH line size 0x8 (8)brand index 0x0 (0)brand id 0x00 (0): unknownfeature information (1/edx):x87 FPU on chip truevirtual-8086 mode enhancement truedebugging extensions truepage size extensions truetime stamp counter trueRDMSR and WRMSR support truephysical address extensions truemachine check exception trueCMPXCHG8B inst. trueAPIC on chip trueSYSENTER and SYSEXIT truememory type range registers truePTE global bit truemachine check architecture trueconditional move/compare instruction truepage attribute table truepage size extension trueprocessor serial number falseCLFLUSH instruction truedebug store falsethermal monitor and clock ctrl falseMMX Technology trueFXSAVE/FXRSTOR trueSSE extensions trueSSE2 extensions trueself snoop truehyper-threading / multi-core supported falsetherm. monitor falseIA64 falsepending break event falsefeature information (1/ecx):PNI/SSE3: Prescott New Instructions truePCLMULDQ instruction true64-bit debug store falseMONITOR/MWAIT falseCPL-qualified debug store falseVMX: virtual machine extensions trueSMX: safer mode extensions falseEnhanced Intel SpeedStep Technology falsethermal monitor 2 falseSSSE3 extensions truecontext ID: adaptive or shared L1 data falseFMA instruction trueCMPXCHG16B instruction truexTPR disable falseperfmon and debug falseprocess context identifiers truedirect cache access falseSSE4.1 extensions trueSSE4.2 extensions trueextended xAPIC support trueMOVBE instruction truePOPCNT instruction truetime stamp counter deadline trueAES instruction trueXSAVE/XSTOR states trueOS-enabled XSAVE/XSTOR trueAVX: advanced vector extensions trueF16C half-precision convert instruction trueRDRAND instruction truehypervisor guest status truecache and TLB information (2):0x63: data TLB: 1G pages, 4-way, 4 entries0x03: data TLB: 4K pages, 4-way, 64 entries0x76: instruction TLB: 2M/4M pages, fully, 8 entries0xff: cache data is in CPUID 40xb5: instruction TLB: 4K, 8-way, 64 entries0xf0: 64 byte prefetching0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entriesprocessor serial number: 0003-06C3-0000-0000-0000-0000deterministic cache parameters (4):--- cache 0 ---cache type data cache (1)cache level 0x1 (1)self-initializing cache level truefully associative cache falseextra threads sharing this cache 0x0 (0)extra processor cores on this die 0x0 (0)system coherency line size 0x3f (63)physical line partitions 0x0 (0)ways of associativity 0x7 (7)ways of associativity 0x0 (0)WBINVD/INVD behavior on lower caches falseinclusive to lower caches falsecomplex cache indexing falsenumber of sets - 1 (s) 63--- cache 1 ---cache type instruction cache (2)cache level 0x1 (1)self-initializing cache level truefully associative cache falseextra threads sharing this cache 0x0 (0)extra processor cores on this die 0x0 (0)system coherency line size 0x3f (63)physical line partitions 0x0 (0)ways of associativity 0x7 (7)ways of associativity 0x0 (0)WBINVD/INVD behavior on lower caches falseinclusive to lower caches falsecomplex cache indexing falsenumber of sets - 1 (s) 63--- cache 2 ---cache type unified cache (3)cache level 0x2 (2)self-initializing cache level truefully associative cache falseextra threads sharing this cache 0x0 (0)extra processor cores on this die 0x0 (0)system coherency line size 0x3f (63)physical line partitions 0x0 (0)ways of associativity 0x7 (7)ways of associativity 0x0 (0)WBINVD/INVD behavior on lower caches falseinclusive to lower caches falsecomplex cache indexing falsenumber of sets - 1 (s) 511--- cache 3 ---cache type unified cache (3)cache level 0x3 (3)self-initializing cache level truefully associative cache falseextra threads sharing this cache 0x0 (0)extra processor cores on this die 0x0 (0)system coherency line size 0x3f (63)physical line partitions 0x0 (0)ways of associativity 0xf (15)ways of associativity 0x6 (6)WBINVD/INVD behavior on lower caches falseinclusive to lower caches truecomplex cache indexing truenumber of sets - 1 (s) 8191MONITOR/MWAIT (5):smallest monitor-line size (bytes) 0x0 (0)largest monitor-line size (bytes) 0x0 (0)enum of Monitor-MWAIT exts supported falsesupports intrs as break-event for MWAIT falsenumber of C0 sub C-states using MWAIT 0x0 (0)number of C1 sub C-states using MWAIT 0x0 (0)number of C2 sub C-states using MWAIT 0x0 (0)number of C3 sub C-states using MWAIT 0x0 (0)number of C4 sub C-states using MWAIT 0x0 (0)number of C5 sub C-states using MWAIT 0x0 (0)number of C6 sub C-states using MWAIT 0x0 (0)number of C7 sub C-states using MWAIT 0x0 (0)Thermal and Power Management Features (6):digital thermometer falseIntel Turbo Boost Technology falseARAT always running APIC timer truePLN power limit notification falseECMD extended clock modulation duty falsePTM package thermal management falseHWP base registers falseHWP notification falseHWP activity window falseHWP energy performance preference falseHWP package level request falseHDC base registers falsedigital thermometer thresholds 0x0 (0)ACNT/MCNT supported performance measure falseACNT2 available falseperformance-energy bias capability falseextended feature flags (7):FSGSBASE instructions trueIA32_TSC_ADJUST MSR supported trueSGX: Software Guard Extensions supported falseBMI instruction trueHLE hardware lock elision falseAVX2: advanced vector extensions 2 trueFDP_EXCPTN_ONLY falseSMEP supervisor mode exec protection trueBMI2 instructions trueenhanced REP MOVSB/STOSB trueINVPCID instruction trueRTM: restricted transactional memory falseQM: quality of service monitoring falsedeprecated FPU CS/DS trueintel memory protection extensions falsePQE: platform quality of service enforce falseAVX512F: AVX-512 foundation instructions falseAVX512DQ: double quadword instructions falseRDSEED instruction falseADX instructions falseSMAP: supervisor mode access prevention falseAVX512IFMA: fused multiply add falseCLFLUSHOPT instruction falseCLWB instruction falseIntel processor trace falseAVX512PF: prefetch instructions falseAVX512ER: exponent reciprocal instrs falseAVX512CD: conflict detection instrs falseSHA instructions falseAVX512BW: byte word instructions falseAVX512VL: vector length falsePREFETCHWT1 falseAVX512VBMI: vector byte manipulation falseUMIP: user-mode instruction prevention falsePKU protection keys for user-mode falseOSPKE CR4.PKE and RDPKRU/WRPKRU falseBNDLDX/BNDSTX MAWAU value in 64-bit mode 0x0 (0)RDPID: read processor D supported falseSGX_LC: SGX launch config supported falseAVX512_4VNNIW: neural network instrs falseAVX512_4FMAPS: multiply acc single prec falseDirect Cache Access Parameters (9):PLATFORM_DCA_CAP MSR bits 0Architecture Performance Monitoring Features (0xa/eax):version ID 0x1 (1)number of counters per logical processor 0x4 (4)bit width of counter 0x30 (48)length of EBX bit vector 0x7 (7)Architecture Performance Monitoring Features (0xa/ebx):core cycle event not available trueinstruction retired event not available truereference cycles event not available truelast-level cache ref event not available truelast-level cache miss event not avail truebranch inst retired event not available truebranch mispred retired event not avail trueArchitecture Performance Monitoring Features (0xa/edx):number of fixed counters 0x0 (0)bit width of fixed counters 0x0 (0)x2APIC features / processor topology (0xb):--- level 0 (thread) ---bits to shift APIC ID to get next 0x0 (0)logical processors at this level 0x1 (1)level number 0x0 (0)level type thread (1)extended APIC ID 2--- level 1 (core) ---bits to shift APIC ID to get next 0x0 (0)logical processors at this level 0x1 (1)level number 0x1 (1)level type core (2)extended APIC ID 2XSAVE features (0xd/0):XCR0 lower 32 bits valid bit field mask 0x00000007XCR0 upper 32 bits valid bit field mask 0x00000000XCR0 supported: x87 state trueXCR0 supported: SSE state trueXCR0 supported: AVX state trueXCR0 supported: MPX BNDREGS falseXCR0 supported: MPX BNDCSR falseXCR0 supported: AVX-512 opmask falseXCR0 supported: AVX-512 ZMM_Hi256 falseXCR0 supported: AVX-512 Hi16_ZMM falseIA32_XSS supported: PT state falseXCR0 supported: PKRU state falsebytes required by fields in XCR0 0x00000340 (832)bytes required by XSAVE/XRSTOR area 0x00000340 (832)XSAVE features (0xd/1):XSAVEOPT instruction trueXSAVEC instruction falseXGETBV instruction falseXSAVES/XRSTORS instructions falseSAVE area size in bytes 0x00000000 (0)IA32_XSS lower 32 bits valid bit field mask 0x00000000IA32_XSS upper 32 bits valid bit field mask 0x00000000AVX/YMM features (0xd/2):AVX/YMM save state byte size 0x00000100 (256)AVX/YMM save state byte offset 0x00000240 (576)supported in IA32_XSS or XCR0 XCR0 (user state)64-byte alignment in compacted XSAVE falsehypervisor_id VMwareVMware0x40000001 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000002 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000003 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000004 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000005 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000006 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000007 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000008 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x40000009 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000a 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000b 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000c 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000d 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000e 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x000000000x4000000f 0x00: eax0x00000000 ebx0x00000000 ecx0x00000000 edx0x00000000hypervisor generic timing information (0x40000010):TSC frequency (Hz) 3392143bus frequency (Hz) 66000extended feature flags (0x80000001/edx):SYSCALL and SYSRET instructions trueexecution disable true1-GB large page support trueRDTSCP true64-bit extensions technology available trueIntel feature flags (0x80000001/ecx):LAHF/SAHF supported in 64-bit mode trueLZCNT advanced bit manipulation true3DNow! PREFETCH/PREFETCHW instructions falsebrand Intel(R) Core(TM) i7-4770 CPU 3.40GHzL1 TLB/cache information: 2M/4M pages L1 TLB (0x80000005/eax):instruction # entries 0x0 (0)instruction associativity 0x0 (0)data # entries 0x0 (0)data associativity 0x0 (0)L1 TLB/cache information: 4K pages L1 TLB (0x80000005/ebx):instruction # entries 0x0 (0)instruction associativity 0x0 (0)data # entries 0x0 (0)data associativity 0x0 (0)L1 data cache information (0x80000005/ecx):line size (bytes) 0x0 (0)lines per tag 0x0 (0)associativity 0x0 (0)size (KB) 0x0 (0)L1 instruction cache information (0x80000005/edx):line size (bytes) 0x0 (0)lines per tag 0x0 (0)associativity 0x0 (0)size (KB) 0x0 (0)L2 TLB/cache information: 2M/4M pages L2 TLB (0x80000006/eax):instruction # entries 0x0 (0)instruction associativity L2 off (0)data # entries 0x0 (0)data associativity L2 off (0)L2 TLB/cache information: 4K pages L2 TLB (0x80000006/ebx):instruction # entries 0x0 (0)instruction associativity L2 off (0)data # entries 0x0 (0)data associativity L2 off (0)L2 unified cache information (0x80000006/ecx):line size (bytes) 0x40 (64)lines per tag 0x0 (0)associativity 8-way (6)size (KB) 0x100 (256)L3 cache information (0x80000006/edx):line size (bytes) 0x0 (0)lines per tag 0x0 (0)associativity L2 off (0)size (in 512KB units) 0x0 (0)Advanced Power Management Features (0x80000007/edx):temperature sensing diode falsefrequency ID (FID) control falsevoltage ID (VID) control falsethermal trip (TTP) falsethermal monitor (TM) falsesoftware thermal control (STC) false100 MHz multiplier control falsehardware P-State control falseTscInvariant truePhysical Address and Linear Address Size (0x80000008/eax):maximum physical address bits 0x2d (45)maximum linear (virtual) address bits 0x30 (48)maximum guest physical address bits 0x0 (0)Logical CPU cores (0x80000008/ecx):number of CPU cores - 1 0x0 (0)ApicIdCoreIdSize 0x0 (0)(multi-processing synth): none(multi-processing method): Intel leaf 0xb(APIC widths synth): CORE_width0 SMT_width0(APIC synth): PKG_ID2 CORE_ID0 SMT_ID0(synth) Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm内容较多以下就是TBL cache and TLB information (2):0x63: data TLB: 1G pages, 4-way, 4 entries0x03: data TLB: 4K pages, 4-way, 64 entries0x76: instruction TLB: 2M/4M pages, fully, 8 entries0xff: cache data is in CPUID 40xb5: instruction TLB: 4K, 8-way, 64 entries0xf0: 64 byte prefetching0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
CPU生成一个虚拟地址------MMU从TBL获取页表转化成物理地址-----MMU将物理地址发送给L1/L2/L3------L1/L2/L3将地址对应数据返回给CPU
