服务器和网站维护,天水做网站的,网架加工工厂图片,网站广告接入锁相环#xff08;PLL#xff09;是一种常用的频率、相位追踪算法#xff0c;在信号解调、交流并网等领域有着广泛的应用。本文对全数字锁相环的原理进行介绍#xff0c;随后给出 verilog 实现及仿真。
PLL 锁相原理 锁相环结构如下图所示#xff0c;主要由鉴相器、环路滤… 锁相环PLL是一种常用的频率、相位追踪算法在信号解调、交流并网等领域有着广泛的应用。本文对全数字锁相环的原理进行介绍随后给出 verilog 实现及仿真。
PLL 锁相原理 锁相环结构如下图所示主要由鉴相器、环路滤波器、压控振荡器等构成 其中鉴相器是一个乘法器设参考信号 u i u_i ui 、本地信号 u o u_o uo 均为正弦信号 u i ( t ) c o s ( ω 1 t φ 1 ) u_i(t)cos(\omega_1 t\varphi_1) ui(t)cos(ω1tφ1) u o ( t ) c o s ( ω 2 t φ 2 ) u_o(t)cos(\omega_2 t\varphi_2) uo(t)cos(ω2tφ2) 根据积化和差公式 u i u_i ui 与 u o u_o uo 的乘积将包含 ω 1 ω 2 \omega_1\omega_2 ω1ω2 和 ω 1 − ω 2 \omega_1-\omega_2 ω1−ω2 两个频率分量经过 LF 低通滤波后将仅剩两者的差频信号 u c c o s [ ( ω 1 − ω 2 ) t ( φ 1 − φ 2 ) ] c o s [ 2 π ( f 1 − f 2 ) t ( φ 1 − φ 2 ) ] \begin{aligned} u_ccos[(\omega_1-\omega_2)t(\varphi_1-\varphi_2)]\\ cos[2\pi(f_1-f_2)t(\varphi_1-\varphi_2)] \end{aligned} uccos[(ω1−ω2)t(φ1−φ2)]cos[2π(f1−f2)t(φ1−φ2)] 使用 f 2 f 0 K 0 u c f_2f_0K_0 u_c f2f0K0uc 控制压控振荡器数字式的一般用 DDS 技术生成的频率即可完成锁相。 假设输入信号相对于基准频率 f 0 f_0 f0 存在 Δ f \Delta f Δf 的频率偏差则完成锁相后两信号将具有固定的相位偏差 Δ φ \Delta \varphi Δφ关系如下 Δ f K 0 c o s ( Δ φ ) \Delta fK_0cos(\Delta \varphi) ΔfK0cos(Δφ) 当然也应当注意到这里的 Δ φ \Delta \varphi Δφ 符号无法被确定。
verilog 实现 PLL 模块主程序如下
/* * file : ADPLL.v* author : 今朝无言* lab : WHU-EIS-LMSWE* date : 2023-08-03* version : v1.0* description : 锁相环* Copyright © 2023 WHU-EIS-LMSWE, All Rights Reserved.*/
module ADPLL(
input clk,
input rst_n,input signed [15:0] A, //参考信号
input signed [15:0] B, //本地信号output signed [15:0] df //频偏
);parameter CLK_FREQ 1_000_000; //采样频率reg signed [15:0] df 16d0;//-----------------------multi---------------------------------
reg signed [31:0] multi 32d0;always (posedge clk) beginif(~rst_n) beginmulti 32d0;endelse beginmulti A*B;end
end//------------------------FIR---------------------------------
wire signed [15:0] multi_filt [1:3];localparam FIR_N 20; //FIR阶数wire [16*(FIR_N1)-1:0] FIR_params;FIR_params_0d1 FIR_params_inst(.params (FIR_params)
);wire clk_div10;
wire clk_div100;clkdiv #(.N(10)) clkdiv10(.clk_in (clk),.clk_out (clk_div10)
);clkdiv #(.N(100)) clkdiv100(.clk_in (clk),.clk_out (clk_div100)
);//低通滤波 多级低通滤波中间穿插下采样
FIR_filter #(.N(FIR_N 1))
FIR_filter_inst1(.clk (clk),.rst_n (rst_n),.filter_params (FIR_params),.data_in (multi[31:16]),.data_out (multi_filt[1])
);//低通滤波
FIR_filter #(.N(FIR_N 1))
FIR_filter_inst2(.clk (clk_div10),.rst_n (rst_n),.filter_params (FIR_params),.data_in (multi_filt[1]),.data_out (multi_filt[2])
);//低通滤波
FIR_filter #(.N(FIR_N 1))
FIR_filter_inst3(.clk (clk_div100),.rst_n (rst_n),.filter_params (FIR_params),.data_in (multi_filt[2]),.data_out (multi_filt[3])
);//---------------------control---------------------------------
always (posedge clk_div100) begindf multi_filt[3]; // dfK*multi_filt此处省略鉴相灵敏度K外部请自行设置合理的K值s
endendmodule低通滤波器及其参数代码如下
/* * file : FIR_filter.v* author : 今朝无言* lab : WHU-EIS-LMSWE* date : 2023-07-03* version : v1.0* description : FIR 滤波器*/
module FIR_filter(
input clk,
input rst_n,input [16*N-1:0] filter_params,input signed [15:0] data_in,
output reg signed [15:0] data_out
);parameter N 32; //滤波器参数个数
parameter div_N 16; //sum结果除 2^div_N作为 filter 的输出//FIR 滤波器参数
reg signed [15:0] b[0:N-1];integer m;
always (*) beginfor(m0; mN; mm1) beginb[m] filter_params[(m 4) : 16];end
endreg signed [15:0] shift_reg[0:N-1];integer i;
always (posedge clk) beginif(~rst_n) beginfor(iN-1; i0; ii-1) beginshift_reg[i] 16d0;endendelse beginfor(iN-1; i0; ii-1) beginshift_reg[i] shift_reg[i-1];endshift_reg[0] data_in;end
endreg signed [31:0] multi[0:N-1];integer j;
always (*) beginfor(j0; jN; jj1) beginmulti[j] shift_reg[j] * b[j];//这里可以考虑使用multiplier IP核使用LUT搭建而这里直接乘使用的是DSP资源一般的FPGA芯片只有几百个end
endreg signed [47:0] sum;integer k;
always (*) beginsum 0;for(k0; kN; kk1) beginsum sum multi[k];end
endalways (posedge clk) begindata_out sum[47-div_N : 32-div_N];
endendmodule/* * file : FIR_params.v* author : 今朝无言* lab : WHU-EIS-LMSWE* date : 2023-08-04* version : v1.0* description : FIR 滤波器 lowpass N20 fc0.1 fs*/
module FIR_params_0d1(
output [335:0] params
);assign params[15:0] 16h0000;
assign params[31:16] 16h0057;
assign params[47:32] 16h0131;
assign params[63:48] 16h0302;
assign params[79:64] 16h0616;
assign params[95:80] 16h0A6D;
assign params[111:96] 16h0FA8;
assign params[127:112] 16h1518;
assign params[143:128] 16h19E1;
assign params[159:144] 16h1D28;
assign params[175:160] 16h1E53;
assign params[191:176] 16h1D28;
assign params[207:192] 16h19E1;
assign params[223:208] 16h1518;
assign params[239:224] 16h0FA8;
assign params[255:240] 16h0A6D;
assign params[271:256] 16h0616;
assign params[287:272] 16h0302;
assign params[303:288] 16h0131;
assign params[319:304] 16h0057;
assign params[335:320] 16h0000;endmodule关于 FIR 滤波器这部分可以参考我之前的博文。
仿真 仿真测试代码如下
timescale 100ns/1nsmodule PLL_tb();reg clk_1M 1b1;
always #5 beginclk_1M ~clk_1M;
endreg rst_n 1b1;//---------------------参考信号A-------------------------------
wire [15:0] A_out_tmp;
wire signed [15:0] A_out; //参考信号localparam f0 24d10_000;
localparam df -24d9; //频率偏差DDS #(.Freq(1_000_000)
)
DDS_inst1(.clk (clk_1M),.rst_n (rst_n),.fout (f0df),.phase0 (16d0),.sin_out (A_out_tmp)
);assign A_out A_out_tmp - 16d32768;//---------------------本地信号B-------------------------------
wire [15:0] B_out_tmp;
wire signed [15:0] B_out;wire signed [23:0] df2; //控制本地信号的频偏DDS #(.Freq (1_000_000)
)
DDS_inst2(.clk (clk_1M),.rst_n (rst_n),.fout (f0df2),.phase0 (16d0),.sin_out (B_out_tmp)
);assign B_out B_out_tmp - 16d32768;//-----------------------PLL---------------------------------
wire signed [15:0] df_PLL;ADPLL #(.Freq (1_000_000)
)
PLL_inst(.clk (clk_1M),.rst_n (rst_n),.A (A_out), //参考信号.B (B_out), //本地信号.df (df_PLL) //频偏
);assign df2 df_PLL/64;//-----------------------tb---------------------------------
initial beginrst_n 1b0;#5000;rst_n 1b1;#100;#1000000;$stop;
endendmoduleDDS 代码如下
/* * file : DDS.v* author : 今朝无言* Lab : WHU-EIS-LMSWE* date : 2023-05-17* version : v1.0* description : 根据给定频率输出正弦信号* Copyright © 2023 WHU-EIS-LMSWE, All Rights Reserved.*/
module DDS(
input clk,
input rst_n,input [23:0] fout, //输出正弦波的频率 1k-10M 要24位
input [15:0] phase0, //初相output [15:0] sin_out
);parameter Freq 100_000_000; //clk频率Hz//-----------------相位累加器-----------------------
reg [47:0] int_f_16 48d0; //相位累加器x-16定点数
wire [55:0] dphi_16; //相位步进//dphi*Freqfout*T, T65536
assign dphi_16 (fout 32)/Freq;always (posedge clk or negedge rst_n) beginif(~rst_n) beginint_f_16 48d0;endelse beginint_f_16 int_f_16 dphi_16;end
end//-----------------正弦查找表-----------------------
wire [15:0] phase;sin_gen sin_gen_inst(.clk (clk),.phase (phase), //相位.sin_out (sin_out)
);assign phase phase0 (int_f_16 16);endmodule相应的正弦查找表如下该模块使用线性插值的方法在仅少量增加资源消耗的情况下将量化误差缩小了两个数量级这部分也可详见我之前的博文
/* * file : sin_gen.v* author : 今朝无言* Lab : WHU-EIS-LMSWE* date : 2023-05-17* version : v1.0* description : 根据给定相位输出正弦信号* Copyright © 2023 WHU-EIS-LMSWE, All Rights Reserved.*/
module sin_gen(
input clk,input [15:0] phase, //相位0~65535对应[0~2pi)
output [15:0] sin_out
);//---------------------正弦查找表-------------------------
wire [7:0] addr1;
wire [7:0] addr2;
wire [15:0] sin_dat1;
wire [15:0] sin_dat2;//sin rom, 16bit, 256 depth
sin_rom sin_rom_inst1(.clka (clk),.addra (addr1),.douta (sin_dat1)
);sin_rom sin_rom_inst2(.clka (clk),.addra (addr2),.douta (sin_dat2)
);//-----------线性插值获取更精确的相位分辨率-------------------
assign addr1 (phase8);
assign addr2 (phase8)1;wire [15:0] phase1;
wire [15:0] phase2;assign phase1 addr18;
assign phase2 addr28;reg [15:0] phase_d0;
reg [15:0] phase_d1; //由于rom数据2拍后才给出因此phase需要与之同步
reg [15:0] phase1_d0;
reg [15:0] phase1_d1;always (posedge clk) beginphase_d0 phase;phase_d1 phase_d0;phase1_d0 phase1;phase1_d1 phase1_d0;
endwire [31:0] multi;
assign multi (sin_dat2 sin_dat1)? (sin_dat2 - sin_dat1)*(phase_d1 - phase1_d1) : (sin_dat1 - sin_dat2)*(phase_d1 - phase1_d1);assign sin_out (sin_dat2 sin_dat1)? sin_dat1 (multi 8) : sin_dat1 - (multi 8);endmodule仿真结果如下
